import chisel3._
import chisel3.util._
import _root_.circt.stage.ChiselStage

class Gen_cnt extends Module {
  val io = IO(new Bundle {
    val din   = Input(UInt(1.W))
    val outa  = Output(UInt(8.W))
    val outb  = Output(UInt(8.W))
    val dout  = Output(UInt(1.W))
  })

  // 返回计数器的函数
  def genCounter(n: Int) = {
      val cntReg = RegInit(0.U(8.W))
      cntReg := Mux(cntReg === n.U, 0.U, cntReg + 1.U)
      cntReg
  }
  
  // 可以直接用这个的函数创建各种不同上限的计数器
  io.outa := genCounter(10)
  io.outb := genCounter(99)

  val shiftReg = RegInit(0.U(4.W))
  shiftReg := Cat(shiftReg(2, 0), io.din)
  io.dout := shiftReg(3)

}

//object Max3 extends App {
//  println(getVerilogString(new Max3()))
//}
object Gen_cnt extends App {
  ChiselStage.emitSystemVerilogFile(
  new Gen_cnt(),
  firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
  )
}
